EE/CS Coursework at UC Berkeley

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Spring 2025

• Electrical Engineering 194: Integrated Circuits Design Project: 16nm SoC
  • Chipyard, Chisel, RISC-V Saturn Core, RoCC Integration, Physical Design and Exploration
• Electrical Engineering 198: Advanced PCB Engineering
  • Altium Designer, High-Speed Digital Circuits, Advanced Routing and Power Design
• Compsci 302: Designing Computer Science Education
  • Computer Science Pedagogy, Curriculum Design, Exam Creation
• Compsci 195: Social Implications of Computer Technology
  • Professional Ethics, Artificial Intelligence, Copyright and Intellectual Property

Teaching: (UCS2 Undergraduate TA) Compsci 61C Discussion Lead

Fall 2024

• EECS 151LA: Application-Specific Integrated Circuits (ASIC) Laboratory

  • Verilog, VLSI Flow, RTL Synthesis and Simulation, P&R Optimizations
  • Project: 3-Stage Pipelined RISC-V Processor with 4 KiB Direct-Mapped Cache (Write-Back Policy) with 64B Cache Lines

• Compsci 170: Efficient Algorithms and Intractable Problems

  Topics

  • Theory: Asymptotics, Recurrence Relations, Divide-and-Conquer, Greedy Algorithms, Dynamic Programming

  • Graphs: DFS, BFS, MST (Prim, Kruskal), Strongly-Connected Components (Kosaraju), Topological Sort, Shortest-Path Algorithms (Dijkstra, Bellman-Ford)

  • Optimization: Linear Programming, Network Flow (Ford-Fulkerson, Edmunds-Karp), Bipartite Matching, Gradient Descent, Zero-Sum Games

  • NP-Complete Reduction Proofs: 3-SAT, 3-Coloring, Vertex / Set Cover, Maximum Independent Set, Hamiltonian Paths, Hamiltonian Cycles, Integer Programming

Teaching: (UCS2 Undergraduate TA) Compsci 61C Exam Development

Summer 2024

Teaching: (UCS2 Undergraduate TA) Compsci 61C Discussion Development

Spring 2024

• Compsci 162: Operating Systems and System Programming
  • Processes and IO, Concurrency (Threads, Processes, Mutexes, Semaphores, Monitors), OS Scheduling, Priority Inversion and Deadlock, Virtual Memory, Demand Paging, Filesystems, Distributed Computing
• EECS 151: Digital Design and Integrated Circuits
  • Combinational Logic, Finite-State Machines, CMOS Circuits, Circuit Timing, Adders / Multipliers / Shifters, Clock Distribution
• EECS 151LB: Field-Programmable Gate Array (FPGA) Laboratory
  • Digital Logic Synthesis, Communication Protocols (FIFO, UART), Input Conditioning (Synchronizer, Edge-Detector, Debouncer)
  • Project: 3-Stage Pipelined RISC-V Processor with MMIO UART Communication

Teaching: Compsci 61C Academic Intern

Onwards…

I have taken many more classes! They will be updated soon.